Latching selector for selectively drawing out a single signal from among a plurality thereof

ABSTRACT

A latching selector comprises a plurality of switching circuits each switching an assigned signal, a memory circuit including bistable circuits and controlling the respective switching circuits, and the same plurality of key switches triggering the memory circuit. The switching circuits have respective signal input terminals supplied with respective assigned signals, respective control terminals and a common signal output terminal. The memory circuit includes memory output terminals respectively connected to the control terminals, memory input terminals respectively connected to the key switches, a number of bistable circuits equal to the digit number sufficient for binary notation of the plurality number, and a coding and encoding matrix connecting the memory input and output terminals to the bistable circuits in binary relation. When a key switch is actuated, the bistable circuits memorize in binary notation which key switch has been actuated, and in turn keep the corresponding switching circuit to conduct the assigned signal to signal output terminal until another key switch is next actuated.

Witd ttes tent [1 1 lisii et al.

[111 3 7 [451 Sept. 18, 19

[54] LATCllllNG SELECTOR FOR SELECTWELY DRAWlNG OUT A SllNGlLE SIGNALFROM AMONG A PLURALITY THEREOF lnventors: Sigeki Isii, Hamamatsu; YnsujiUchiyama, l-lanakita, both of Japan Nippon Galtki Seizo KahushikiKaisha, Shizuoka-ken, Japan Filed: Aug. 8, 1972 Appl. No.: 278,824

[73] Assignee:

[5 6] References Cited UNITED STATES PATENTS 12/1959 Munch, Jr 307/243 111/1963 Campbell, Jr.... 307/243 2/1968 McNicol 340/147 LP 1/1970Hiyoshi 84/1.0l

Primary ExaminerJ0hn W. Caldwell Assistant Examiner-Robert .l. MooneyAttorney-Solon B. Kemon et al.

[57] ABSTRACT A latching selector comprises a plurality of switchingcircuits each switching an assigned signal, a memory circuit includingbistable circuits and controlling the respective switching circuits, andthe same plurality of key switches triggering the memory circuit. Theswitching circuits have respective signal input terminals supplied withrespective assigned signals, respective control terminals and a commonsignal output terminal. The memory circuit includes memory outputterminals respectively connected to the control terminals, memory inputterminals respectively connected to the key switches, a number ofbistable circuits equal to the digit number sufficient for binarynotation of the plurality number, and a coding and encoding matrixconnecting the memory input and output terminals to the bistablecircuits in binary relation. When a key switch is actuated, the bistablecircuits memorize in binary notation which key switch has been actuated,and in turn keep the corresponding switching circuit to conduct theassigned signal to signal output terminal until another key switch isnext actuated.

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KEYER OUTPUT LATCHING SELECTOR KEY SWITCH I I I KEY SWITCH F FIG.5

sm a nr 3 ml Q PATENTED SEP1 8 I973 LATCIIING SELECTOR lFOR SELECTIVELYDRAWING OUT A SINGLE SIGNAL FROM AMONG A PLURALITY THEREOF BACKGROUND OFTHE INVENTION This invention relates to a latching selector forselectively drawing out a single signal from a plurality of signals andmore particularly to a latching selector adapted fordetermining pedaltones in an electronic musical instrument.

The pedal tone generator arrangement of an electronic musical instrumentis provided with a latching selector for selectively drawing out a tonesignal from tone generators which corresponds to a depressed pedal keyand sustaining the drawing out of the tone signal until another pedalkey is next operated. The latching selector is so constructed that therecan be derived from tone generators a single tone signal'correspondingto only one of plural pedal keys even when they are simultaneouslyoperated.

A prior art latching selector set forth, for example, in

the US. Pat. No. 3,488,515 issued to Teruo I-Iiyoshi on Jan. 6, 1970includes one bistable or flip-flop circuit for one tone, and isnecessarily provided with 13 flip-flop circuits for 13 pedal keys. Withthe above-mentioned latching selector, opeation of a pedal key reversesthe state of the corresponding flip-flop circuit to derive a tone signalfrom the corresponding tone generator and prevents the flip-flopcircuits corresponding to all the other pedal keys from delivering tonesignal from the tone generators corresponding to the other pedal keys.However, a latching selector requiring a large number of flip-flopcircuits as described above is unavoidably complicated in constructionan destitute of reliability in operation. It is accordingly the objectof this invention to provide a latching selector which well serves thepurpose with a smaller number of bistable circuits than the tonegenerators and consequently admits of a much simpler arrangement.

' SUMMARY OF THE INVENTION According to one aspect of this inventionthere is provided a latching selector for selectively deriving an inputsignal from a plurality of input signals, which comprises a plurality ofswitching circuits each having a signal input terminal, a controlterminal and a signal output terminal connected in common to all theswitching circuits; a memory circuit including the same plu rality ofmemory output terminals respectively connected to the control terminalsof the switching circuits, the same plurality of memory input terminals,a number of bistable circuits equal to the digit number sufficient forbinary notation of the plurality number and each having'a first and asecond lines, and a coding and encoding matrix connecting the memoryoutput and input terminals to either ofthe first and the second lines ofthe respective bistable circuits in a binary code fashion; the sameplurality of key switches respectively connected to the respectivememory input terminals; and a control voltage source connected to thekey switches and having a voltage sufficient for deciding the stages ofthe bistable circuits.

In accordance with this invention the number of the bistable circuitscan be less than that of the input signals from which a single inputsignal is selectively derived. The key switches may be comprised byswitches each having a normally open contact, normally closed contactand movable contact. The switches may be connected in preference circuitfashion in such a manner that a movable contact" of one of the switchesis connected to a normally closed fixed contact of the ad- 5 jacentswitch, the normally open fixed contacts of the respective switchesbeing connected to the corresponding input terminals of the memorycircuit, the movable contact of the rearmost switch being connected tothe control voltage source. With such switch arrangement, even whenseveral switches are simultaneously actuated a single input signal canbe selected corresponding to one of the actuated switches.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an arrangement of a latchingselector according to this invention;

FIG. 2 is an arrangement for producing bass tone signals of anelectronic musical instrument including a latching selector;

FIG. 3 is a circuit diagram of a latching selector according to anembodiment of this invention;

FIG. 4 shows a circuit diagramof a bistable circuit usable for thelatching selector of FIG 3; and

FIG. 5 is a circuit diagram of a latching selector according to anotherembodiment of the invention.

DESCRIPTION-OF THE PREFERRED EMBODIMENTS Referring to FIG. ll, referencenumeral 1 represents a plurality of switching circuits. The switchingcircuits 1 have signal input terminals 11 to In, control terminals II toJn and a commonv signal output terminal 0. The input terminals 1! to Inare connected to receive input signals from signal sources. Numeral 2denotes memory circuit including memory input terminals Ll to Ln andmemory output terminals Ml to Mn. The respective output terminals Ml toMn are connected to the respective control terminals II to Jn of thecorresponding switching circuits. The memory circuit 2 has its inputterminals Ll to Ln connected to key switches Kl to Kn which in turnconnected to a control voltage source, and includes, as later described,a smaller number of bistable or flip-flop circuits than the signalsources. The

output terminals Ml to Mn of the memory circuit 2 are connected todifferent selective combinations of one of the two output terminals ofthe respective flip-flop circuits in a binary coded fashion. Therefore,any one of the output terminals of the memory circuit 2 may be set at adifferent voltage level representing a so-called memorized state fromthose appearing at the remaining output terminals of the memory circuit2. Accordingly, only one switching circuit that is connected to theabove-mentioned one output terminal of the memory circuit 2 conducts aninput signal supplied to the input terminal to the common outputterminal 0. The input terminals of the memory circuit 2 are connected tothe same selective combinations of one of the two output terminals ofthe respective flip-flop circuits as those to which there are connectedthe corresponding output terminals of the memory circuit 2. Where,therefore, one of the switches K1 to K13 is actuated, then there isimpressed a control voltage on the corresponding lines of the flip-flopcircuits which are connected to the actuated switch, setting thememorizing states of the flip-flop circuits. As a result, the outputterminal of the memory circuit 2 corresponding to the actuated switchhas a different voltage level from those of the other output terminalsof the memory circuit 2, causing the corresponding switching circuit toconduct an input signal from the input terminal to the output terminal.Thus this state is continued until another of the aforesaid switches Klto K13 is operated.

The latching selector of this invention may be applied to an electronicmusical instrument, for example, with an arrangement shown in FIG. 2.The latching selector is connected to thirteen signal sources or tonegenerators representing, for example, notes C4 through C5 and also tothe key switches actuated by thirteen pedal keys. A tone signal pickedup by the latching selector has its frequency divided by eight (i.e.stepped down by three octaves by three frequency dividers or flip-flopcircuits and the divided tone signal or bass tone signal is conducted toa keyer. Since the latching selector has, as described above, amemorizing faculty, the tone signal selected thereby continues to besupplied to a keyer via the frequency dividers. The keyer is socontrolled, as indicated in FIG. 2, by key switches as to produce thebase tone signal at the output side thereof upon depression of a pedalkey. l

There will now be described a latching selector according to anembodiment of this invention shown in FIG. 3 with reference made toFIG. 1. The parts of FIG. 3 the same as those of FIG. 1 are denoted bythe same numerals. The memory circuit 2 comprises four bistable circuitsor flip-flop circuits 20, 21, 22 and 23, each having first and secondlines a and b. Each'flip-flop circuit may consist of an ordinary typeincluding two transistors Trl and Tr2 as illustrated in FIG. 4. Thefirst and second lines a and b are led out from the collectors of thetransistors Trl and Tr2 respectively. These transistors Trl and Tr2 havetheir emitters connected to a negative power source (l2V) and theircollectors to the ground terminal (B) through resistors. As is wellknown, while the first line a of the flip-flop circuit has a firstvoltage level, for example, l2V, its second line b indicates a secondvoltage level, for example, a ground potential, or vice versa.

The 13 output terminals M1 to M13 of the memory circuit 2 are connectedthrough diodes to one of the two lines aand b of the respectiveflip-flop circuits with different selective combinations constituting anindividual-to-binary convertor matrix. For example, the output terminalM1 of the memory'circuit 2 is connected through diodes D0, D1, D2 and D3to the first lines a of the flip-flop circuits 20, 21, 22 and 23,representing 0000 code. The output terminal M2 is connected throughdiodes to the second line b of the flipflop circuit and the first linesa of the flip-flop circuits 21, 22 and 23, representing 0001 code.Theoretically, one of the two lines of each of the four flip-flopcircuits 20, 21, 22 and 23 can be selectively combined in 16 ways atmaximum. In FIG. 3, however, there are used thirteen combinations inconsideration of application to an electronic musical instrument.

The output terminals M1 to M13 of the memory circuit 2 are connected tothe controls .II to I13 of the switching circuits 1, each of whichincludes a transistor Tr3 having its base connected to the correspondingtone signal input terminal I through a resistor, R1, its emitterconnected to the power source (l2V) and its collector grounded through aload resistor RL. The collector of the transistor Tr3 is furtherconnected to the common output terminal 0 through a take-out resistorR0.

The input terminals L1 to L13 of the memory circuit 2 are connected toits output terminals M1 to M13 and the key switches K1 to K13. Each ofthe key switches Kl to K13 may include a normally closed fixed contact,a normally open fixed contact and a movable contact. Further, these keyswitches Kl to K13 may be connected in a preference network fashion suchthat the movable contact of one of them is connected to the normallyclosed fixed contact of the adjacent key switch. The normally open fixedcontact of the key switch is connected to the coresponding inputterminal L of the memory circuit 2. In this case the movable contact ofthe rearmost key switch K13 is connected to the control voltage source(12V).

There will now be described the operation of the latching selector ofFIG. 3. Now let it be assumed that initially, the first lines a of theflip-flop circuits 20, 21, 22 and 23 have a first voltage level (12V)and the second lines b indicate a second voltage level (0V). Under thiscondition, the first output terminal M1 connected only to the firstlines a of the flip-flop circuits 20, 21, 22 and 23 becomes free fromany urging voltages, whereas all the other output terminals M2 to M13 ofthe memory circuit 2 are given a ground potential via at least one diodeconnected to the b line(s). That is, the output terminal M2, forexample, is connected to the second line b of the flip-flop circuit 20now exhibiting the ground potential. And the output terminal M12 isconnected to the second lines b of the flip-flop circuits 20, 21 and 23.Under such condition, the transistors Tr3 which are included in theswitching circuits 1 corresponding to the output terminals M2 to M13having a ground potential are brought in a saturated state. Accordingly,input tone signals supplied to the input terminals I2 to I13 can not bedrawn out of the collectors of these saturated transistors Tr3.

On the other hand, the first output terminal M1 of the memory circuit 2does not have a ground potential, and is consequence the transistor Tr3of the switching circuit 1 connected to the first output terminal M1 isnot saturated. Therefore, a tone signal supplied to the first inputterminal ll of the switching circuit 1 is conducted to the outputteriminal 0 from the collector of the transistor Tr3 through thetake-out resistor R0.

Where the key switch K2 is operated by the corresponding pedal key (notshown), the input terminal L2 of the memory circuit 2 is impressed withcontrol voltage (l2V). In this case, the memorizing state of theflip-flop circuit 20 whose second line b is connected to the inputterminal L2 is reversed, that is, the first line a is set at the secondvoltage level (0V) and the second line b at the first voltage level (12V). At this time, the states of the remaining flip-flop circuits 21, 22and 23 remains unchanged. Accordingly, the output terminal M2 isreleased from the ground potential and the output terminal M1 is nowbrought to the ground potential. Therefore, a tone signal supplied tothe input terminal I2 of the switching circuit 1 corresponding to theoutput terminal M2 is conducted to the common output terminal 0. Thisstate is maintained until another key switch is actuated. Where there isactuated next time, for example, the key switch K12, then there arisesthe reversion of the states of the other flip-flop circuits 21 and 23whose second lines b is connected to the input terminal L12. As theresult, the output terminal M2 is now brought to the ground potential,preventing the tone signal supplied to the input terminal I2 from beingconducted to the common output terminal 0, but the output terminal M12is released from the ground potential thereby permitting a tone signalimpressed on the input terminal I12 corresponding to the output terminalM12 to appear at the common output terminal 0.

If the key switches K1 to K13 are connected in a preference fashion asdescribed above, then a tone signal supplied only to a signal inputterminal corresponding to one of key switches actuated simultaneouslynearest to K13 will be delivered to the common output terminal even whenseveral pedal keys are depressed at the same time.

FIG. shows the arrangement of a latching selector according to a secondembodiment of this invention using field effect transistors. Accordingto this embodiment, the flip-flop circuits 20 to 23 and switchingcircuits 1, as well as the diodes D0 to D3 of FIG. 3 are comprised byMOS field effect transistors.

The output terminals M1 to M13 of the memory circuit 2 are connectedthrough MOS field effect transistors QrO, Orll, Qr2 and Qr3 to the sameselective combinations of the linesa and b of the four flip-flopcircuits 20, 21, 22 and 23 as in FIG. 3. Between the output terminal Mlof the memory circuit 2 and the ground are connected conduction pathsformed between the source and drain of the field effect transistors Qrttto Qr3. The gates of the MOS field effect transistors Ortl to Or?) areconnected to the first lines a of the flip-flop circuits 20 to 23. Theother output terminals M2 to M13 are connected to either of the twolines of the re spective flip-flop circuits 20 to 23 constituting abinary coding matrix.

The input terminals L1 to L13 of the memory 2 are connected through theMOS field effect transistors Qm0 to Qm3 to the same selectivecombinations of the two lines of the four flip-flop circuits 211 to 23as in FIG. 3. The input terminal L1, forexample, is connected to thegates of the MOS field effect transistors Qm0 to 0013, whose conductionpaths in turn are connected between the first lines a of the flip-flopcircuits 20 to 23 and the ground. The input terminals L1 to L13 of thememory circuits 2 are grounded through the resistor R3 and connected tothe normally open fixed contacts of the corresponding key switches K1 toK13.

The output terminals M1 to M13 of the memory circuit 2 are connected tothe control terminals 11 to J 13 of the switching circuits 1. Thesecontrol terminals J1 to .113 are connected to the input signal paths ofthe switching circuits 1 such that the MOS field effect transistorsOr(). to Qr3 connected to the corresponding output terminals shunt theinput signal paths of the switching circuits 1 to the ground.

There will now be described the operation of the latching selector ofFIG. 5 arranged as described above. Let it be assumed that initially,the first lines a of the flip-flop circuits 20 to 23 are set at a firstvoltage level (now 0V) and the second lines b thereof at a secondvoltage level (now 12V). Under this condition, the MOS field effecttransistors Qr0 to Or3 connected to the output terminal Ml of the memorycircuit 2 remain nonconducting. Accordingly, the signal path of theswitching circuit 1 supplied with a tone signal through the inputterminal I1 is not short-circuited, causing the tone signal supplied tothe input terminal l1 to be drawn out to the common output terminal 0.The remaining output terminals M2 to M13 of the memory circuit 2 areshunted to the ground through at least one MOS field effect transistorwhich is rendered conductive by being connected to the second lines b ofthe flip-flop circuits 20 to 23. Under this condition, the signal pathof the corresponding switching circuit is short-circuited to the ground,preventing an input tone signal from being conducted to the commonoutput terminal 0.

Where there is operated next time, for example, the key switch K2, theinput terminal L2 of the memory 2 is impressed with a control voltage(-1 2V). As the result, the MOS field effect transistor connected to theinput terminal L2 and the second line b of the flip-flop circuit 21)becomes conducting, causing the second line b to have a groundpotential. Accordingly, the memorizing state of the flip-flop circuit 20is reversed. That is, the first line a of the flip-flop circuit 20 isset at the second voltage level (1 2V) and the second line b at thefirst voltage level (0V). Thus the MOS field effect transistor Qrt)which is connected to the output terminal M1 of the memory circuit 2 andhas been remained nonconducting up to this time is now renderedconductive to short-circuit the signal path related to'the inputterminal I1of the switching circuit 1 to the ground. On the other hand,that MOS field effect transistor which is connected to the outputterminal M2 of the memory circuit 2 and thesecond line b of theflip-flop circuit 20 and has been kept conducting up to this time is nowturned nonconducting. At this time, the states of the remainingflip-flop circuits 21 to 23 remains unchanged. As the result, the signalpath related to the input terminal I2 of the switching circuit 1 ischanged from the short-circuited to the nonshort-circuited state,permitting a tone signal supplied to the input terminal I2 to appear atthe common output terminal 0. This condition is sustained until anotherkey switch is actuated.

What we claim is:

1. A latching selector for selectively drawing out a single signal froma plurality of signals comprising:

a. a plurality of switching circuits each having a signal inputterminal, a control terminal and a signal output terminal;

b. a memory circuit including same said plurality of memory outputterminals respectively connected v to said control terminals, same saidplurality of memory input terminals, bistable circuits in a number equalto the digit number sufficient for binary notation of said pluralitynumber and each having a first and a second lines, and a coding andencoding matrix connecting said memory output terminals and said memoryinput terminals to either of said first and second lines of saidrespective bistable circuits in a binary code fashion;

c. same said plurality of key switches respectively connected to saidrespective memory input terminals; and I d. and a control voltage sourceconnected to said key switches and having a voltage sufficient fordeciding the states of said bistable circuits.

2. A latching selector according to claim 1 wherein said means forcoupling said output and input terminals of said memory circuit to saidlines of said bistable circuits are diodes.

3. A latching selector according to claim 1 wherein each said key switchincludes a normally open fixed contact, a normally closed fixed contactand a movable contact, and wherein said key switchesare connected in apreference fashion in such a manner that said movable contact of therespective key switches is connected to the normally closed fixedcontact of the adjacent key switch, and the movable contact of therearmost switch to said control voltage source, said normally opencontacts of the respective switches being connected to the correspondinginput terminals of said memory circuit.

4. A latching selector according to claim 1 wherein each said switchingcircuit includes a transistor having a collector, an emitter and a base,and the respective input terminals of said switching circuit and therespective output terminals of said memory circuit are coupled to thebases of the corresponding transistors.

5. A latching selector according to claim 1 wherein said memory circuitincludes four bistable circuits, thirteen output terminals and thirteeninput terminals; and said key switches connected to said input terminalseach including a normally open fixed contact, a normally closed fixedcontact and a movable contact, said normally open fixed contact beingconnected to the corresponding input terminal of said memory circuit,said movable contact to the normally closed contact of the adjacent keyswitch and the movable contact of the rearmost key switch to saidcontrol voltage source.

6. A latching selector according to claim 1 wherein said coding andencoding matrix includes first coupling elements connected in a binarycode matrix fashion between said memory output terminals and said linesof the bistable circuits and second coupling elements connected in abinary code matrix fashion between said memory input terminals and saidlines of the bistable circuits.

7. A latching selector according to claim 6 wherein said first andsecond coupling elements each have a conduction path and a controlelectrode for controlling the conductivity of said conduction path bythe voltage impressed on said control electrode, the conduction path ofsaid first coupling elements being connected between the correspondingmemory output terminals and a circuit ground and their controlelectrodes being connected to the corresponding lines of said bistablecircuits, said first coupling elements being rendered conductive whensaid lines of said bistable circuits to which said control electrodesare connected are set at a first voltage level, the conduction paths ofsaid second coupling elements being connected between said lines of saidbistable circuits and a circuit ground and their control electrodesbeing connected to said memory input terminals, said second couplingelements being rendered conductive when said memory input terminals towhich said control electrodes are connected are impressedwith thevoltage from said control voltage source.

8. A latching selector according to claim 7 wherein said first andsecond coupling elements are field effect transistors each having aconduction path formed between a source and a drain and a gate forcontrolling the conductivity of said conduction path by a voltageimpressed thereon.

patent No. 3,760,358 Dated September 18, 1973 Inventor( s) Sigeki IsiiIt is'certified that error appears in the above-identified patent andthat said Letters Patent are hereby corrected as shown below:

[30] Priority Benefit:

Japanese Patent Application 59601/71, filed August 9, 1 971 V Signed andsealed this 29th day of October 197% (SEAL) Attest:

McCOY M. GIBSON JR; C. MARSHALL DANN Attesting Officer Commissioner ofPatents FORM PO-105O (10-69) USCOMM DC 6o376 p69 I v I u.s. GOVERNMENTPRINTING orncz; I965 0--3G6-334.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3 ,760358 Dated September 18 1973 Inventor( s) geki Isii It is 'certified thaterror appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

[30] Priority Benefit:

Japanese Patent Application 59601/71, filed August 9, 1971 Signed andsealed this 29th day of October 1971 (SEAL) Attest:

MCCOY M. GIBSON JR. C. MARSHALL 'DANN Attesting Officer Commissioner ofPatents FORM PO-1050 (10-69) USCOMNHDC 6376 P6g u.s. GOVERNMENT PRINTINGOFFICE: I969 o-ass-sam

1. A latching selector for selectively drawing out a single signal froma plurality of signals comprising: a. a plurality of switching circuitseach having a signal input terminal, a control terminal and a signaloutput terminal; b. a memory circuit including same said plurality ofmemory output terminals respectively connected to said controlterminals, same said plurality of memory input terminals, bistablecircuits in a number equal to the digit number sufficient for binarynotation of said plurality number and each having a first and a secondlines, and a coding and encoding matrix connecting said memory outputterminals and said memory input terminals to either of said first andsecond lines of said respective bistable circuits in a binary codefashion; c. same said plurality of key switches respectively connectedto said respective memory input terminals; and d. and a control voltagesource connected to said key switches and having a voltage sufficientfor deciding the states of said bistable circuits.
 2. A latchingselector according to claim 1 wherein said means for coupling saidoutput and input terminals of said memory circuit to said lines of saidbistable circuits are diodes.
 3. A latching selector according to claim1 wherein each said key switch includes a normally open fixed contact, anormally closed fixed contact and a movable contact, and wherein saidkey switches are connected in a preference fashion in such a manner thatsaid movable contact of the respective key switches is connected to thenormally closed fixed contact of the adjacent key switch, and themovable contact of the rearmost switch to said control voltage source,said normally open contacts of the respective switches being connectedto the corresponding input terminals of said memory circuit.
 4. Alatching selector according to claim 1 wherein each said switchingcircuit includes a transistor having a collector, an emitter and a base,and the respective input terminals of said switching circuit and therespective output terminals of said memory circuit are coupled to thebases of the corresponding transistors.
 5. A latching selector accordingto claim 1 wherein said memory circuit includes four bistable circuits,thirteen output terminals and thirteen input terminals; and said keyswitches connected to said input terminals each including a normallyopen fixed contact, a normally closed fixed contact and a movablecontact, said normally open fixed contact being connected to thecorresponding input terminal of said memory circuit, said movablecontact to the normally closed contact of the adjacent key switch andthe movable contact of the rearmost key switch to said control voltagesource.
 6. A latching selector according to claim 1 wherein said codingand encoding matrix includes first coupling elements connected in abinary code matrix fashion between said memory output terminals and saidlines of the bistable circuits and second coupling elements connected ina binary code matrix fashion between said memory input terminals andsaid lines of the bistable circuits.
 7. A latching selector according toclaim 6 wherein said first and second coupling elements each have aconduction path and a control electrode for controlling the conductivityof said conduction path by the voltage impressed on said controlelectrode, the conduction path of said first coupling elements beingconnected between the corresponding memory output terminals and acircuit ground and their control electrodes being connected to thecorresponding lines of said bistable circuits, said first couplingelements being rendered conductive when said lines of said bistablecircuits to which said control electrodes are connected are set at afirst voltage level, the conduction paths of said second couplingelements being connected between said lines of said bistable circuitsand a circuit ground and their control electrodes being connected tosaid memory input terminals, said second coupling elements beingrendered conductive when said memory input terminals to which saidcontrol electrodes are connected are impressed with the voltage fromsaid control voltage source.
 8. A latching selector according to claim 7wherein said first and second coupling elements are field effecttransistors each having a conduction path formed between a source and adrain and a gate for controlling the conductivity of said conductionpath by a voltage impressed thereon.